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DATASHEET
PCI CLOCK GENERATOR Description
The MK1493-03B is a general purpose clock generator device that provides an integrated clocking solution for PCI /networking applications. It provides eight individually programmable PCI clocks, one CPU clock, three additional fixed PCI clocks, and a 25 MHz reference clock for LAN support. This part incorporates IDT's newest clock technology, offering more robust features and functionality. The device provides a gradual transition from its initial clock frequency to the new one. Using a serially programmable SMBus interface, the MK1493-03B can select the output clock frequency and the transition from the original value to the new value. The SMBus also allows each of the 8 programmable PCI clocks to be individually enabled and disabled.
MK1493-03B Features
* Individually programmable (25, 33.33, 50, 66.66 MHz) * * * * * * * * * * * * *
PCI clocks (Serial or external pin control) 1 CPU clock at 100/125 MHz Selectable; single ended/differential selectable 1 Clock at 66.66 MHz 1 Clock at 66/71/83 MHz selectable 1 Clock at 50 MHz 25 MHz reference clock SMBus Programming Power-up default frequency can be selected through FS inputs 25 MHz crystal or clock input required PCICLK cycle to cycle jitter <250 ps CPUCLK cycle to cycle jitter <150 ps 48-pin, 240 mil TSSOP Package Operating Voltage 3.3 V 5% Commercial (0 to +70C) and Industrial temperature ranges (-40 to +85C)
Block Diagram
VDD 7 8 SCLK SDATA FS(0:7)_A FS(0:7)_B FS8 FS9 FS10 X1/CLK 25 MHz X2 External caps required with crystal for accurate tuning of the clock 7 GND Clock Buffer/ Crystal Ocsillator REF25(25MHz) 8 8 PLL Divider Buffer Circuits SMBus Programmable PCICLK(0:7) Each PCI Output Clock Individually Programmable CPUCLK 100M/125M CPUCLKB 100M/125M CLK66M/71M/83M CLK66M CLK50M
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Pin Assignment
FS3_A FS2_A FS1_A FS0_A GND VDD SCL SDA GND X1 / ICLK X2 VDD REF25 VDD GND GND VDD CPUCLK CPUCLK FS7_B CLK50M FS6_B FS5_B FS4_B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-pin TSSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 FS4_A FS5_A FS6_A FS7_A FS0_B FS1_B PCICLK7 GND VDD PCICLK6 PCICLK5 PCICLK4 FS2_B VDD GND CLK66/71/83 CLK66M/FS8 FS3_B VDD GND PCICLK2/FS10 PCICLK1/FS9 PCICLK0 PCICLK3
Table 1. Frequency Select
FS(0:7)_B 0 0 1 1
1)
FS(0:7)_A 0 1 0 1
PCICLK(0:7)* 1 2 25 MHz 33.3333 MHz 50 MHz 66.6666 MHz
Each PCI clock is individually selectable.
Table 2. Input Select (FS8, FS9,FS10&FS11)
FS8 (pin 32) 0 1 FS9 (pin 27) 0 0 1 1
2)
CPUCLK/CPUCLK 2 125MHz 100MHz3
FS10 (pin 28) 0 1 0 1
CLK66M/71M/83M 2 (pin 33) 83.33 MHz3 71.42 MHz 66.66 MHz OFF
The changes in frequency are step changes.
3) Default Value upon Power up.
Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name FS3_A FS2_A FS1_A FS0_A GND VDD SCL SDA GND X1/ICLK X2 VDD Pin Type Input Input Input Input Power Power Input Input Power Input XO Power Pin Description Freq select input pin for PCI CLK3 per table 1. Internal pull-up resistor 120K. Freq select input pin for PCI CLK2 per table 1. Internal pull-up resistor 120K. Freq select input pin for PCI CLK1 per table 1. Internal pull-up resistor 120K. Freq select input pin for PCI CLK0 per table 1. Internal pull-up resistor 120K. Connect to ground. Connect to +3.3 V. Clock pin for SMBus circuitry, 5 V tolerant. Data pin for SMBus circuitry, 5 V tolerant. Connect to ground. Crystal connection/input clock. Connect to a 25 MHz fundamental mode crystal or clock input. Connect to a 25 MHz fundamental mode crystal or leave open for clock input. Connect to +3.3 V.
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Pin Number 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Name REF25 VDD GND GND VDD CPUCLK CPUCLK FS7_B CLK50M FS6_B FS5_B FS4_B PCICLK3 PCICLK0 PCICLK1/FS9 PCICLK2/FS10 GND VDD FS3_B CLK66M/FS8 CLK66/71/83 GND VDD FS2_B PCICLK4 PCICLK5 PCICLK6 VDD GND PCICLK7 FS1_B FS0_B FS7_A FS6_A FS5_A FS4_A
Pin Type
Pin Description
Output Buffered reference output of 25 MHz, (See table2, FS11=0 turns this clock off). Power Power Power Power Connect to +3.3 V. Connect to ground. Connect to ground. Connect to +3.3 V.
Output 100/125 MHz CPU clock. Output 100/125 MHz CPU clock. Input 1 of 4 freq select input pin for PCI CLK7 per table 1. Internal pull-up resistor 120 K.
Output 50 MHz clock output. Input Input Input Freq select input pin for PCI CLK6 per table 1. Internal pull-up resistor 120 K. Freq select input pin for PCI CLK5 per table 1. Internal pull-up resistor 120 K. Freq select input pin for PCI CLK4 per table 1. Internal pull-up resistor 120 K.
Output PCI CLK3 (Programmable PCI Clock 3). Output PCI CLK0 (Programmable PCI Clock 0). I/O I/O Power Power Input I/O PCI CLK1 (For CLK66/71/83 selection on pin 33, using FS9) (See table 2). PCI CLK2 (For CLK66/71/83 selection on pin 33, using FS10) (See table 2). Connect to ground. Connect to +3.3 V. Freq select input pin for PCI CLK3 per table 1. Internal pull-up resistor 120 K. 66.66 MHz clock, FS8=1 CPUCLK=100 MHz, FS8=0 CPUCLK=125 MHz) (table 2).
Output Clock66/71/83. Default Value is 83.33 MHz. Power Power Input Connect to ground. Connect to +3.3 V. Freq select input pin for PCI CLK2 per table 1. Internal pull-up resistor 120 K.
Output PCI CLK4 (Programmable PCI Clock 4). Output PCI CLK5 (Programmable PCI Clock 5). Output PCI CLK6 (Programmable PCI Clock 6). Power Power Connect to +3.3 V. Connect to ground.
Output PCI CLK7. Input Input Input Input Input Input Freq select input pin for PCI CLK1 per table 1. Internal Pull up resistor 120 K. Freq select input pin for PCI CLK0 per table 1. Internal Pull up resistor 120 K. Freq select input pin for PCI CLK7 per table 1. Internal Pull up resistor 120 K. Freq select input pin for PCI CLK6 per table 1. Internal Pull up resistor 120 K. Freq select input pin for PCI CLK5 per table 1. Internal Pull up resistor 120 K. Freq select input pin for PCI CLK4 per table 1. Internal Pull up resistor 120 K.
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Power Groups
Pin Number VDD 12 30, 40 35 6 17 14 GND 9 29, 41 34 5 16 15 Ref, Crystal Osc Power supply PCICLK PCI 66 clocks SMBus CPU Clocks(100MHz) PLL P Description O O O
Index Block Write Operation Beginning Byte N ACK X Byte O O O Byte N + X - 1 ACK stoP
General SM-Bus Serial Interface Information
How to Write:
* * * * * * * * * *
Controller (host) sends a start bit Controller (host) sends the write address D2 (H) IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller sends Byte Count X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit
Index Block Write Operation Controller (Host) T Slave Address D2
(H)
IDT (Slave/Receiver)
starT WR
ACK Beg Location = N ACK Data Byte Count = X ACK
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How to Read:
* * * * * * * * * * * * * *
Controller (host) will send a start bit Controller (host) sends the write address D2 (H) IDT clock will acknowledge Controller (host) sends the beginning Byte location = N IDT clock will acknowledge Controller (host) will send a repeat start bit Controller (host) sends the read address Byte D3 (H) IDT clock will acknowledge IDT clock will send the data Byte count = X IDT clock sends Byte N IDT clock sends Byte N+X-1 Controller (host) will need to acknowledge each Byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Read Operation Controller (Host) T Slave Address D2 (H) starT bit WR =0 ACK Beginning Loc = N ACK RT Slave Address D2 (H) repeat starT RD =1 ACK Data Byte Count=X ACK Beginning Byte N ACK O O O N P NAK stoP bit X B Y T E S O O O Byte N + X - 1 IDT (Slave/Receiver)
SMBus Table 3: Read-Back Register
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Frequency Selection See Frequency table 4 FS vs. SMBus prog Name Control Function RESERVED HW/SW select RESERVED RW HW SW Type 0 1 Power UP State 0 0 0 0 0 0 0 0
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SMBus Table 3 (cont.): Output Enable Control Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 39 38 37 31 28 27 26 Name PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable Power UP State 1 1 1 1 1 1 1 1
SMBus Table 3 (cont.): Output Enable Control Register
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 32 33 13 19 18 21 CLK66 CLK66/71/83 REF25 CPUCLK CPUCLK CLK50 Name Control Function RESERVED RESERVED Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Type 0 1 Power UP State 0 0 1 1 1 1 1 1
SMBus Table 3 (cont.): Frequency Control Register
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 4 44 3 43 2 36 1 31 Name Control Function FS0_A FS0_B FS1_A FS1_B FS2_A FS2_B FS3_A FS3_B Type RW RW RW RW RW RW RW RW See Frequency Table 1 0 1 Power UP State X X X X X X X X
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SMBus Table 3 (cont.): Frequency Control Register
Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 48 24 47 23 46 22 45 20 Control Function FS4_A FS4_B FS5_A FS5_B FS6_A FS6_B FS7_A FS7_B Type RW RW RW RW RW RW RW RW See Frequency Table 1 0 1 Power UP State X X X X X X X X
SMBus Table 3 (cont.): Frequency Control Register
Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Control Function FS8 FS9 FS10 RESERVED RESERVED RESERVED RESERVED RESERVED Type RW RW RW 0 CPU=125M 1 CPU=100M Power UP State 1 0 0 0 1 1 1 1
00=83.33M, 01=71.42M 10=66.66M, 11=OFF
SMBus Table 3 (cont.): Reserved
Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Type 0 1 Power UP State 1 1 1 1 1 1 1 1
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SMBus Table 3 (cont.): Vendor and Revision ID Register
Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Control Function RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Type R R R R R R R R VENDOR ID 0 REVISION 1 Power UP State 0 0 1 0 0 0 0 1
SMBus Table 3 (cont.): Byte Count Register
Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Control Function BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Type RW RW RW RW RW RW RW RW 0 1 Power UP State 0 0 0 0 1 0 0 0
Writing to this Register will confirm how many bytes will be read back, default 08=8 bytes
SMBus Table 3 (cont.): Reserved
Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Type 0 1 Power UP State 1 1 1 1 1 1 1 1
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SMBus Table 3 (cont.): Programming Enable
Byte 10 Bit 7 Pin # Name Programming M/N Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Control Function Enables prog bytes 11-12 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Type RW 0 Disabled 1 Enabled Power UP State 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RW RW RW RW RW RW RW
0 0 0 0 0 0 0
SMBus Table 3 (cont.): MN
Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Bit 8 The decimal representation of M Div(6:0) is equal to reference divider value. default Powerup=latch-in or Byte o ROM table. Type RW RW RW RW RW RW RW RW 0 1 Power UP State X X X X X X X X
SMBus Table 3 (cont.): MN
Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function The decimal representation of N Div(8:0) is equal to feedback divider value. default Powerup=latch-in or Byte o ROM table. N Div8 is in byte11 Type RW RW RW RW RW RW RW RW 0 1 Power UP State X X X X X X X X
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Table 4. Frequency Margin Selection through SMBus (Byte 0)
Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4
Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPUCLK 4 CPUCLK (MHz) 100.00/125.00 nominal + 1% nominal + 2% nominal + 3% nominal + 4% nominal + 5% nominal + 6% nominal + 7% nominal + 8% nominal + 9% nominal + 10% nominal + 11% nominal + 12% nominal + 13% nominal + 14% nominal + 15% nominal + 16% nominal + 17% nominal + 18% nominal + 19% nominal +20% nominal +21% nominal +22% nominal +23% nominal +24% nominal +25% nominal - 3% nominal - 5% nominal - 10% nominal - 15% nominal - 20% nominal - 25%
CLK50 (MHz) 4
CLK66, 66/71/83 (MHz) 4 66, 66/71/83 nominal + 1% nominal + 2% nominal + 3% nominal + 4% nominal + 5% nominal + 6% nominal + 7% nominal + 8% nominal + 9% nominal + 10% nominal + 11% nominal + 12% nominal + 13% nominal + 14% nominal + 15% nominal + 16% nominal + 17% nominal + 18% nominal + 19% nominal +20% nominal +21% nominal +22% nominal +23% nominal +24% nominal +25% nominal - 3% nominal - 5% nominal - 10% nominal - 15% nominal - 20% nominal - 25%
PCICLK (MHz) 4
50.00 nominal + 1% nominal + 2% nominal + 3% nominal + 4% nominal + 5% nominal + 6% nominal + 7% nominal+ 8% nominal + 9% nominal + 10% nominal + 11% nominal + 12% nominal + 13% nominal + 14% nominal + 15% nominal + 16% nominal + 17% nominal + 18% nominal + 19% nominal +20% nominal +21% nominal +22% nominal +23% nominal +24% nominal +25% nominal - 3% nominal - 5% nominal - 10% nominal - 15% nominal - 20% nominal - 25%
nominal nominal + 1% nominal + 2% nominal + 3% nominal + 4% nominal + 5% nominal + 6% nominal + 7% nominal + 8% nominal + 9% nominal + 10% nominal + 11% nominal + 12% nominal + 13% nominal + 14% nominal + 15% nominal + 16% nominal + 17% nominal + 18% nominal + 19% nominal +20% nominal +21% nominal +22% nominal +23% nominal +24% nominal +25% nominal - 3% nominal - 5% nominal - 10% nominal - 15% nominal - 20% nominal - 25%
The transition of each of these clock frequencies is gradual.
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External Components
The MK1493-03B requires a minimum number of external components for proper operation.
Figure 1
V ia to V DD
P rogramming Header V ia to G nd Device Pad 2K
Decoupling Capacitor
Decoupling capacitors of 0.1F and 0.001F must be connected between each VDD and GND (pins 12&9, 30&29, 40&41, 35&34, 6&5, 17&16, 14&15) as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
8.2K C lock trace to load S eries Term. R es.
Series Termination Resistor
When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 .
To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10Kilo ohm (10 K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 above shows a means of implementing this function when a switch or 2-pin header is used. With no jumpers installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used.
Shared Pin Operation- Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level(voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads.
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1493-03B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
Item
Max Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature 5.5 V -0.5 V to VDD+0.5 V 0 to +70 C -40 to +85 C -65 to +150 C 125 C 260 C
Rating
Parameter
Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Power Supply Voltage (measured in respect to GND)
Min.
0 -40 +3.15
Typ.
Max.
+70 +85
Units
C C V
3.3
+3.45
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V5%, Ambient Temperature -40 to +85 C
Parameter
Input High Voltage Input Low Voltage Input High Current Input Low Current
Symbol
VIH VIL IIH IIL1 IIL2
Conditions
Min.
2
Typ.
Max.
0.8
Units
V V A A A
VIN=VDD VIN=0V, SDA, SCL no pull-up resistors. VIN=0V, All other inputs with pull-up resistors CL = full load
-5 -5 -200 155 25
5
Supply Current Input Frequency Pin Inductance Input Capacitance
IDD FIN LPIN CIN COUT CINX
mA MHz 7 nH pF pF pF ms 5 6 5 3
Logic inputs Output pin capacitance X1 and X2 pins From VDD Power-up
CLK Stabilization
TSTAB
Electrical Characteristics - Input
Unless stated otherwise, VDD = 3.3 V5%, CL=20 pF Ambient Temperature -40 to +85 C
Parameter
Input Frequency SM Bus clock
Symbol
FIN SCL
Conditions
Crystal or clock input SM Bus clock
Min.
Typ.
25 100
Max. Units
MHz 110 KHz
Electrical Characteristics - CPUCLK (Single-ended)
Unless stated otherwise, VDD = 3.3 V5%, CL=20 pF Ambient Temperature -40 to +85 C
Parameter
Output Frequency Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle C-C Jitter Single ended
Symbol
FO1 RDSP VOH VOL tr tf dt
Conditions
VO = VDD*(0.5) IOH = -12 mA, IOL = 12 mA, VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Measured @ VDD/2 Measured @ VDD/2
Min.
12 2.4
Typ.
100
Max. Units
MHz 55 V
0.3 2.0 3.0 45 50 150
0.4
V ns ns
55
% ps
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Electrical Characteristics - CPUCLK, CPUCLK (CMOS complimentary)
Unless stated otherwise, VDD = 3.3 V5%, CL= 20 pF, Ambient Temperature 0 to +70 C
Parameter
Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time VCM Duty Cycle Jitter, Cycle-to-Cycle Output to Output Skew between CPU to CPU clocks
Symbol
ZO VOH2B VOL2B
Conditions
Vo=Vx
Min.
15 2.4
Typ.
Max. Units
55 0.4V Ohms V V ns ns V 55 % ps
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Common Mode Voltage Measured @ VDD/2 Measured @ VDD/2 Measured @ VDD/2
2 2
2 3 1.5
45 110 50
Electrical Characteristics - CPUCLK, CPUCLK (CMOS complimentary)
Unless stated otherwise, VDD = 3.3 V5%, CL= 20 pF, Ambient Temperature -40 to +85 C
Parameter
Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time VCM Duty Cycle Jitter, Cycle-to-Cycle Output to Output Skew between CPU to CPU clocks
Symbol
ZO VOH2B VOL2B
Conditions
Vo=Vx
Min.
15 2.4
Typ.
Max. Units
55 0.4V Ohms V V ns ns V 55 % ps
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Common Mode Voltage Measured @ VDD/2 Measured @ VDD/2 Measured @ VDD/2 45
2 3 1.5 110 50
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Electrical Characteristics - CLK50M, CLK66M & CLK66M/71M/83M
Unless stated otherwise, VDD = 3.3 V5%, CL= 20 pF, Ambient Temperature -40 to +85 C
Parameter
Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Cycle to Cycle Jitter
Symbol
RDSP VOH VOL tr tf
Conditions
VO = VDD*(0.5) IOH = -12 mA IOL = 12 mA VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Measured @ VDD/2 Measured @ VDD/2
Min.
12 2.4
Typ.
Max. Units
55 V V ns ns 55 % ps
0.3 2.0 2.4 45 50 250
0.4
Electrical Characteristics - PCICLK
Unless stated otherwise, VDD = 3.3 V5%, CL=30 pF, Ambient Temperature 0 to +70 C
Parameter
Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Output to Output Skew Cycle to Cycle Jitter
Symbol
RDSP VOH VOL tr tf
Conditions
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V, Measured @ VDD/2 Measured @ VDD/2 Measured @ VDD/2
Min.
12 2.4
Typ.
Max. Units
55 0.55 V V ns ns % ps ps
2.0 2.0 45 50 250 250
2.4 3.0 55
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Electrical Characteristics - PCICLK
Unless stated otherwise, VDD = 3.3 V5%, CL=30 pF, Ambient Temperature -40 to +85 C
Parameter
Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Output to Output Skew Cycle to Cycle Jitter
Symbol
RDSP VOH VOL tr tf
Conditions
VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V, Measured @ VDD/2 Measured @ VDD/2 Measured @ VDD/2
Min.
12 2.4
Typ.
Max. Units
55 0.55 V V ns ns 55 % ps ps
3.0 3.0 45 50 250 250
Electrical Characteristics - 25 MHz Reference
Unless stated otherwise, VDD = 3.3 V5%, CL=20 pF VDD = 3.3 V, Ambient Temperature 0 to +70 C
Parameter
Output Frequency Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Jitter Cycle to Cycle
Symbol
FO RDSP VOH VOL tr tf
Conditions
VO = VDD*(0.5) IOH = -1 mA, IOL = 1 mA, VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Measured @ VDD/2 Measured @ VDD/2
Min.
20 2.4
Typ.
25
Max. Units
MHz 60 0.4 V V ns ns 55 % ps
2.0 2.0 45 50 150
Electrical Characteristics - 25 MHz Reference
Unless stated otherwise, VDD = 3.3 V5%, CL=20 pF VDD = 3.3 V, Ambient Temperature -40 to +85 C
Parameter
Output Frequency Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Jitter Cycle to Cycle
Symbol
FO RDSP VOH VOL tr tf
Conditions
VO = VDD*(0.5) IOH = -1 mA, IOL = 1 mA, VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Measured @ VDD/2 Measured @ VDD/2
Min.
20 2.4
Typ.
25
Max. Units
MHz 60 0.4 V V ns ns 60 % ps
2.0 2.0 40 50 150
IDTTM PCI CLOCK GENERATOR
16
MK1493-03B
REV H 051310
MK1493-03B PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (48-pin TSSOP, 6.10 mm Body, .50mm pitch)
Package dimensions are kept current with JEDEC Publication No. 95
20 48
S YMB O L A A1 A2 b c D E E1 e L aaa Millim e te rs MIN MAX -1 .1 0 0 .0 5 0 .1 5 0 .8 5 1 .0 5 0 .1 7 0 .2 7 0 .0 9 0 .2 0 1 2 .4 0 1 2 .6 0 8 .1 0 B AS IC 6 .0 0 6 .2 0 0 .5 B AS IC 0 .5 0 0 .7 5 0 8 -0 .0 8
E1 INDEX AREA
E
12 D
A2 A1
A
c
-Ce
b SEATING PLANE L
aaa C
Ordering Information
Part / Order Number
MK1493-03BGLF MK1493-03BGLFTR MK1493-03BGILF MK1493-03BGILFTR
Marking
MK1493-03BGLF MK1493-03BGLF 1493-03BGIL 1493-03BGIL
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
48-pin TSSOP 48-pin TSSOP 48-pin TSSOP 48-pin TSSOP
Temperature
0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDTTM PCI CLOCK GENERATOR
17
MK1493-03B
REV H 051310
MK1493-03B PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
ERRATA Changes from MK1493-03 to MK1493-03A Data Sheet
Page 1 The part number changed from MK1493-03 to MK1493-03A FS11 on the block diagram is removed Page 2, Table 2, FS11 column removed Default Output clock value for CLK66M/71M/83M is 83M. Page3 Pin 33 description/function changed from I/O pin to Output pin only. The FS11 input option is deleted Page6 Table 3 Byte2, bit3 (pin13) and bit5 (pin32) changed from Disable upon power upon to Enable upon powerup. Page 7 Table 3 Byte 5, Bit 4 changed from FS11 to reserved Byte 5 bit 5 and 6 changed to 0 upon power up. Page 8 Byte 7 bit 4 changed from 0 to 1 Page 13 SMBUs max clock speed increased from 64KHz to 110KHz Page 17 Ordering Information changed from MK1493-03G to MK1493-03AG
Changes from MK1493-03A to MK1493-03B Data Sheet
Page 1 The part number changed from MK1493-03A to MK1493-03B Page 8 SMBUS vendor Revision ID Byte 7 Power up state changed from o to 1, Bit 4 Power up state changed from 1 to 0 Page 13 The fall time for CPUCLK (single ended) and complimentary the VOL=0.8V changed to VOL=0.4V Page 16 The part ordering number changed from MK1493-03AG to MK1493-03BG; added LF.
IDTTM PCI CLOCK GENERATOR
18
MK1493-03B
REV H 051310
MK1493-03B PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc. www.idt.com
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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